1. Field of the Invention
The present application relates to flexible modular processing systems. More particularly, the present invention relates to a modular random access modified time division multiple access (TDMA) processing system having a TDMA bus and a bus master's systems bus which interconnects a plurality of novel circuit card assemblies (CCAs) having novel interfaces to form a flexible modular distributed processing system.
2. Description of the Prior Art
Heretofore, mainframe computing systems have employed different types of bus structures. Many mainframe computers employ systems or main buses wherein the bus is under control of one user and all of the users of the bus are blocked from using the system bus until the user completes his task. Such system buses are commercially available with standard interface units and protocol to enable designers of custom equipment to interconnect processing systems to a plurality of functional units which carry out predetermined task and to communicate with each other under control of the central processing system (CPU).
A popular commercially available systems bus is sold by Motorola and other vendors under the name Versa Modular European (VME) and VME-2 Bus Systems. This bus structure is combined with VME interface units to permit CPUs, microprocessors and functional units on Circuit Card Assemblies (CCA's) to seize control of the VME systems bus and transmit information to other assemblies on the bus until the bus master controlling the bus relinquishes control to another bus master designated user on the bus.
Since the VME or systems bus by definition operates as a shared bus system, the speed of operation of the processing system connected thereto is somewhat limited.
It is well known to employ Time Division Multiple Access (TDMA) concepts on a data bus. A predetermined number of unique time slots or divisions are established, at least one for each card of functional unit on the bus. Each functional unit has its turn to effectively become bus master during its time slot division whether or not the time slot is to be utilized.
In many processing systems some functional units operate as slave units and seldom need access to the TDMA bus, thus, a large number of time slots are wasted with conventional TDMA bus systems. Another disadvantage of TDMA bus systems is that a change in the number of cards or functional elements on the system may requires a change in the number of predetermined time slots which require a change in the software protocol.
Heretofore CCA's have been connected to systems buses for connection to a CPU in a distributed processing system and connected to each other directly through some form of compatible interface with the use of ribbon cables to provide a path for data that would be too slow for proper use on a systems (VME) bus or to avoid having to write software to replace the data path on the systems bus.
It would be desirable to eliminate the need for ribbon cables and/or custom mother boards used to provide direct paths between CCA's and to provide a modified TDMA bus system which virtually eliminates the waste of time slots and conventional TDMA bus protocol systems and to provide a highly flexible modular bus system which permits the change of position of CCA's in a high speed processing system without a change in protocol or software.